This invention relates to methods for manufacturing semiconductor structures and more particularly to methods for protecting exposed junctions formed in active regions of such semiconductor structures.
As is known in the art it is often desirable to protect exposed junctions formed in active regions of a semiconductor structure from ambient air to contaminants which otherwise may result in changes in electrical characteristics of the structure or failure of devices formed in such structure. Specifically, the air or contaminant particles present on the surface produce surface charges. Such surface charges may result in short circuits across the exposed junction. One technique for providing protection to the junction is to deposit a passivating layer on the exposed surface portion of the junction. This prior art technique presents a significant disadvantage because by depositing a passivating layer on the surface portions of the semiconductor any ambient air or contaminant particles present on the semiconductor surface during formation of such passivation layer will be trapped between the surface of the semiconductor and the deposited passivating layer. The trapped air or contaminant particles still produce surface charges which may result in short circuits across the junction. It is also well known that active regions of certain semiconductor materials such as gallium arsenide (GaAs), may be rendered semi-insulating by ion implantation of particles, such as protons (H.sup.+) or oxygen ions (O.sup.+). There are two distinct physical mechanisms by which ion implantation of particles into portions of a crystal renders such portions semi-insulating. One mechanism is the effect of the impact of such particles on the crystal's lattice structure, since high energy particle impact damages the lattice structure thereby decreasing the electrical conductivity thereof. The second mechanism is the effect of the implanted particles on excess, or free, electrons since implanted particles, such as O.sup.+, act as carrier trap sites which combine with the excess, or free electrons, to provide a net zero charge. Thus the exposed areas of such junctions are rendered semi-insulating and are effectively electrically isolated from the remaining portions of such active regions. Thus, exposure of such formed semi-insulating regions to air or containments will not effect the electrical properties of the remaining electrically isolated portions of such active regions, and hence will substantially prevent one cause of device failure. Generally, implantation depths of 1-2 microns are achieved with high-energy ion beams (i.e. beams having energies greater than 1 million electron volts). A prior art method for rendering portions of the active regions of mesa shaped semiconductors semi-insulating generally includes the following steps: forming a plurality of first contacts on one surface of a substrate; forming an active layer on the opposite surface of such substrate; masking selective portions of the active layer by providing a like plurality of areas of photoresist on such active layer, each area being aligned with a corresponding one of such first contacts on the opposite surface of the substrate; and implanting particles into unmasked portions of the active layer rendering all of such unmasked portions semi-insulating. At this point a support layer is formed over the active layer and the substrate is etched away in selective locations to provide the mesa-shaped semiconductors having semi-insulated surface portions. While this prior art approach may be useful in some applications the step of patterning the layer of photoresist to provide the plurality of areas of photoresist on such active layer, aligned with the top contacts, requires a front to back alignment of the pattern mask with the top contacts. This alignment step is a difficult step which increases processing time and decreases device yield. Further, the maximum depth of penetration by an implant beam of the active region is generally only 1 to 2 microns which is generally sufficient to render semi-insulating thin active layers (1 to 2 microns thick) associated with high frequency semiconductors, but is generally insufficient to render semi-insulating thicker active regions (3 to 6 microns) such as those associated with lower frequency devices.